The present invention relates to a nonvolatile semiconductor memory device and its manufacturing method, and more particularly to techniques of realizing high integration and reliability of a nonvolatile semiconductor memory device capable of electrical programming.
Of electrically programmable nonvolatile semiconductor memory devices, a bulk erasable memory or so-called flash memory is known. Flash memories provide excellent portability and shock resistance and are electrically bulk erasable. For these reasons, demands for flash memories as storage devices of compact portable information apparatuses such as portable personal computers and digital still cameras are rapidly increasing. Reduction in a bit cost by a smaller memory cell area is an important factor for market expansion. Various memory cells realizing this have been proposed, for example, as described in xe2x80x9cOhyo Butsuri (or Applied Physics)xe2x80x9d, Vol. 65, No. 11, pp. 1114-1124 published by the Japan Society of Applied Physics on Nov. 10, 1996 (hereinafter called xe2x80x9cDocument 1xe2x80x9d).
A virtual ground type memory cell utilizing a three-layer polysilicon gate is described, for example, in JP-B-2694618 (registered on Sep. 12, 1997) corresponding to U.S. Pat. No. 5,095,344. This memory cell is constituted of semiconductor regions formed in a well of a semiconductor substrate and three gates. The three gates include a control gate formed on the well and an erase gate formed between the control gate and a floating gate disposed near each other. These three gates are made of polysilicon and are separated by insulator films. The floating gate and well are also separated by an insulator film. The control gate extending in the row direction constitutes a word line. The source/drain diffusion regions are formed along the column direction and are of a virtual ground type that shares the diffusion regions with adjacent memory cells. With this layout, a pitch in the row direction can be reduced. The erase gate is parallel to the channel and disposed between and in parallel to the word lines (control gates). In writing data in a memory cell described in Document 1, independent positive voltages are applied to the word line and drain, and 0 V is applied to the well, source and erase gate. Hot electrons are therefore generated in the channel region near the drain so that electrons are injected into the floating gate and the threshold voltage of the memory cell rises. In erasing data in the memory cell, a positive voltage is applied to the erase gate, and 0 V is applied to the word line, source, drain and well. Electrons are drained from the floating gate into the erase gate so that the threshold voltage lowers.
A split-gate type memory cell is disclosed, for example, in JP-A-9-321157 (laid open on Dec. 12, 1997). In this memory cell, a large overlap is formed between a diffusion layer and a floating gate to raise the floating gate potential by the diffusion layer potential and apply a low voltage to the word line. In this manner, the efficiency of generating and injecting hot electrons during data write can be improved.
A method of controlling the floating gate potential by the word line and controlling the split channel by a third gate different from the floating and control gates is discussed, for example, in the xe2x80x9cTechnical Digestxe2x80x9d at the International Electron Devices Meeting, 1989, pp. 603-606.
The channel length is becoming shorter as the flash memory size reduces. A tradeoff between the breakdown voltage between a diffusion layer and a well and punch-through between a source and a drain becomes an important issue, regardless of the type of a memory cell.
The breakdown voltage between the diffusion layer and well is always required to be about 5V or higher during the write operation for the following reason.
For example, in the cell of the type that data is written by hot electron injection, about 12 V is applied to the control gate and about 5 V or higher is applied to the drain to generate channel hot electrons by utilizing a potential difference between the drain and the source applied with 0 V. The breakdown voltage between the drain and source is required to be the drain voltage or higher.
In the cell of the type that data is written by Fowler-Nordheim tunneling electron injection into the whole channel region, for example, about 18 V is applied to the control gate above the floating gate and 0 V is applied to the source/drain to write data by a tunnel current from the inversion layer to the floating gate. In this case, it is necessary to inhibit data write to other cells of the memory array having the same control gate. To this end, for example, about 5 V or higher is applied to the drains of the data write inhibited cells to float the sources so that the inversion channels having the same potential as the drains can be formed under the floating gates. In this manner, the potential difference between the floating gate and well can be reduced and electron tunneling from the channel to the floating gate can be prevented. In this case, the breakdown voltage between the diffusion layer and well is required to be the drain voltage or higher.
In the cell of the type that data is written by electron emission into the diffusion layer, about xe2x88x9212 V is applied to the control gate of a write cell, about 5 V is applied to the diffusion layer, and 0 V is applied to the well to drain electrons in the floating gate into the diffusion layer to write data. In this case, the breakdown voltage between the diffusion layer and well is required to be the drain voltage or higher. For the write inhibited cell having the same control gate as the write cell, 0 V is applied to the diffusion layer to relax the potential difference between the floating gate and diffusion layer.
As above, the breakdown voltage between the diffusion layer and well is required to be about 5 V or higher.
In a flash memory, when data is read, the threshold voltage of a memory cell is checked by generating a potential difference of about 1 V between the source and drain. It is a requisite that this source-drain voltage will not generate punch-through. Other conditions for preventing punch-through must be satisfied depending on the type of a cell.
For example, in the cell of a hot electron injection type, the memory array has cells having the same drain and source as the write cell or has cells having sources and drains respectively being connected by wiring layers. Such a cell is applied with the same drain voltage and source voltage as the write cell. This cell is generally inhibited to write data. If data write throughput is to be improved by parallel programming of a plurality of memory cells within the current drivability of a power source in the chip, it is necessary to prevent leak current between the source and drain of write inhibited cells. It is therefore necessary to prevent punch-through at the source/drain voltage of about 5 V or higher during hot electron injection.
There is another case of a cell called a virtual ground type cell. In the cell of this type, isolation is performed by using a select gate, control gate or the like. As described earlier, in the data write not utilizing injection, a voltage of about 5 V or hither is applied to the diffusion layer. Isolation of the virtual ground type cell from the voltage of about 5 V or higher applied to the diffusion layer is performed by using the control gate or the like. It is therefore necessary to prevent punch-through relative to the diffusion layer.
Low resistance to punch-through between the source and drain to be caused by a short channel has been avoided by implanting ions in the whole channel region and raising the impurity concentration of the channel region. With this method, however, the impurity concentration of a portion of the channel region in contact with the diffusion layer is raised so that the breakdown voltage is lowered.
According to an embodiment of the invention, a nonvolatile semiconductor memory device is provided which has memory cells each comprising: a well of a first conductivity type formed in a semiconductor substrate; a pair of semiconductor regions of a second conductivity type formed in the well of the first conductivity type, the pair of semiconductor regions being used as a source and a drain; a first gate formed on the semiconductor substrate via a first gate insulator; a second gate formed on a second insulator film covering the first gate; and a third gate formed via the second insulator film relative to the first gate and via a third insulator film relative to the second gate, wherein an impurity doped region of the first conductivity type having an impurity concentration higher than the well is formed in a channel region between the pair of semiconductor regions, the impurity doped region being not in contact with the semiconductor regions.
According to this embodiment, the impurity region having a higher impurity concentration than the well can prevent punch-through. This impurity region having a high impurity concentration is not in contact with the source/drain so that the breakdown voltage is not degraded.
According to another embodiment of the invention, a nonvolatile semiconductor memory device is provided which has memory cells each comprising: a semiconductor substrate having at least a first conductivity type region on a principal surface of the semiconductor substrate; a pair of semiconductor regions of a second conductivity type formed in the first conductivity type region, the pair of semiconductor regions being used as a source and a drain; a first gate formed above a channel region between the semiconductor regions via a first insulator film; and a second gate formed on the first gate via a second insulator film, wherein in a partial area of the channel region, a heavily impurity doped region of the first conductivity type is formed having a higher impurity concentration than the first conductivity type region, and the heavily impurity doped region is spaced from any one of the semiconductor regions.
Similar to the previously described embodiment, also in this embodiment, the heavily impurity doped region can prevent punch through without lowering the breakdown voltage. In each of the embodiments, punch-through can be more reliably prevented by continuously forming the impurity region having a high impurity concentration along the channel width direction or by forming the impurity region deeper than the source/drain.
According to another embodiment, a manufacturing method for a nonvolatile semiconductor memory device is provided which comprises: a step of forming a well of a first conductivity type in a semiconductor substrate; a step of forming a pair of semiconductor regions of a second conductivity type formed in the well of the first conductivity type, the pair of semiconductor regions being used as a source and a drain; a step of forming a first gate on the semiconductor substrate via a first gate insulator; a step of forming a second gate on a second insulator film covering the first gate; and a step of forming an impurity doped region of the first conductivity type having an impurity concentration higher than the well in a channel region between the pair of semiconductor regions, the impurity doped region being not in contact with the semiconductor regions. The semiconductor regions and the impurity region are formed in a self-alignment manner by tilted ion implantation tilted in opposite directions from a normal of the semiconductor substrate, by using the first gate as a mask.
According to this embodiment, the nonvolatile semiconductor memory device can be manufactured by changing only some of the processes without particular photoresist masks.
According to another embodiment of the invention, a manufacturing method for a nonvolatile semiconductor memory device, is provided which comprises: a step of forming dummy gates on a semiconductor substrate having a first conductivity type region on a surface thereof; a step of forming a pair of source/drain diffusion layers of a second conductivity type in a surface layer of the semiconductor substrate between adjacent dummy gates, by using the dummy gates as a mask; a step of burying the dummy gates with a first insulator film; a step of removing a portion of the first insulator film to expose an upper surface of each dummy gate without exposing the surface of the semiconductor substrate; a step of removing the dummy gates; a step of depositing a silicon nitride film or a polysilicon film on an upper surface of the first insulator film and an inner surface of a groove formed in the first insulator film by removing each dummy gate, to the extent that the groove is not completely buried; a step of etching back the silicon nitride film or the polysilicon film to form side walls on an inner surface of each groove; and a step of implanting impurities of the first conductivity type to form a heavily impurity doped region having an impurity concentration higher than the first conductivity type region in the surface layer of the semiconductor substrate between the pair of source/drain diffusion layers, by using the first insulator film and the side walls as a mask.
According to this embodiment, the heavily impurity doped region not in contact with the source/drain can be formed efficiently even for a stacked-type memory cell in which a pair of source/drain regions is formed in surface layers of the semiconductor substrate sandwiching the floating gate. The side walls on the inner surface of the groove are not necessarily required to be formed, but after the deposition step the heavily impurity doped region may be formed by implanting impurity ions of the first conductivity type at an energy allowing the impurity ions to transmit through the silicon nitride film or polysilicon film on the bottom of the groove. In this case, the step of etching back the side walls can be omitted so that processes can be simplified. If not the silicon nitride film but the polysilicon film is used, this polysilicon film can be used later as the floating gate so that processes can be simplified more.
Other objects, features and advantages of the invention will become apparent from the following description of the embodiments of the invention taken in conjunction with the accompanying drawings.